1. Field of the Invention
This invention relates generally to communications within multi-processor computer systems. More specifically, it relates to a bus architecture for connecting multiple reduced instruction set computer (RISC) processors and special purpose Very Large Scale Integration (VLSI) gate arrays.
2. Background Information
Many computer systems today are composed of multiple processing units in order to increase their processing power. These programmable processors often must interact with hardwired logic such as VLSI gate arrays. Some functions of complex computer systems are performed by such hardware because of the increased speed capabilities this hardware provides. However, other functions may be better implemented in software or firmware because of the flexibility software or firmware provides. In a large computer system such as the Extended Processing Complex (XPC), a file cache system designed to operate in conjunction with a 2200 Series computer system, both of which are available from Unisys Corporation, some capabilities of embedded subsystems are implemented in a combination of hardware and software/firmware. These subsystems perform required functions as components of the larger system. These subsystems combine the increased speed of hardware implementations with the flexible nature of programming to efficiently satisfy subsystem requirements.
One of the requirements of these subsystems is to communicate with other systems and components that may have different word sizes for data transferred between systems. For example, the characteristic word size for instructions and data in the 2200 Series computer is 36-bits, but microprocessors in the XPC system operate on 32-bit words. Thus, a device such as the XPC that must communicate with a 2200 Series computer system and various 32-bit devices must be capable of processing data in either format. One way to satisfy this requirement is to duplicate the bus interface between the external systems, the 2200 Series computer, and the XPC. That is, separate interfaces for 32-bit data transfers and 36-bit data transfers could be provided. However, this approach would be more expensive because of the added hardware and may not be possible because of the additional signal lines required. What is desired and most advantageous is a common bus design that fully supports 36-bit or 32-bit data transfers without requiring duplicate signal lines or redundant input/output (I/O) logic.
Attempting to satisfy the requirement by simply adding four data lines to a 32-bit bus would not be sufficient. Since error detection is very important in large fault tolerant systems such as the XPC, the mere addition of four data lines when operating in a 36-bit mode would cause parity errors on data transfers because existing 32-bit parity generation and checking circuitry would not be able to correctly handle 36-bit data transfers. Uniform interface logic is necessary on both sending and receiving ends of the bus to provide effective parity generation and parity checking regardless of whether the bus is being used in 36-bit or 32-bit mode. Such an interface does not exist in the prior art.
There have been various attempts to provide a multiple or variable width data path. In Matick, et. al., U.S. Pat. No. 4,663,729, and Dill, et. al., U.S. Pat. No. 4,667,305, is disclosed a display architecture which supports data path widths of 32, 64, 128, and 256 bits. However, the disclosed system does not provide for extensive parity generation and checking as does the present invention, nor does it support 36-bit data words. A data bus being operable with 8-bit, 16-bit or 32-bit modes is shown in Kinoshita, U.S. Pat. No. 5,113,369. The data bus shown is used in a computer system capable of executing programs containing instructions and data consisting of 16-bit or 32-bit words. This system does not show the use of 32-bit and 36-bit data words or parity generation logic. A dual bit length protocol is described in Frank, U.S. Pat. No. 5,255,376, which is capable of transferring data in 32-bit or 64-bit words. The Frank system is designed to transfer data in one of two word sizes, but the size of one must be twice the size of the other (i.e., 32 and 64). In addition, no parity error detection logic is described. What the prior an is lacking is a bus with associated parity generation and parity checking logic which will transfer either 32-bit or 36-bit data words without using duplicate signal lines.